1. Field of the Invention
Embodiments of the invention are directed to a method and apparatus for sequencing transfer requests from a bus master to a bus slave on a System on Chip (“SOC”) interconnect. In particular, embodiments are directed to a method and apparatus for reducing transfer latency between a bus master and a bus slave by altering the priority of requests in an SOC interconnect.
2. Relevant Background
System-on-chip (SOC) technology operates and controls various types of systems. In general, SOC technology is the assembling of all the necessary electronic circuits and parts for a “system” (such as a cell phone or digital camera) on a single integrated circuit (“IC”), generally known as a microchip.
SOCs typically include initiators, also known as bus masters (for example, processors, graphics engines, direct memory access (“dma”) engines, and the like), bus targets (for example, memory controllers), and system buses, also known as interconnects. To operate the system that the SOC is intended to control, a bus master initiates a transfer request to a target, also known as a slave, via the system bus or interconnect. If multiple masters desire to access a particular slave simultaneously, the requests for these multiple masters must be processed through a central arbiter, or arbitration system. The arbitration system controls the communications between the masters and the slaves; in particular, it controls the order in which the masters communicate with the slaves.
The order in which the masters communicate with the slaves can be important if the requests from the masters are latency, or time, restricted. Typically, each master in the SOC can have a latency requirement for each request. A latency requirement identifies the time constraint, if any, for fulfilling the request. For example, a video engine may be required to write a certain number of frames/second to create a picture or image, and may write these frames from its internal buffer into main memory. If the memory controller, that is, the slave, is unable to accept or service these requests in a timely fashion, the buffer in the video engine will overrun and the picture produced will be incomplete and jagged.
Latency requirements can be dictated by the particular master, or the particular type of request regardless of the master transmitting the request. Although the latency requirements of the request may be critical, in current systems, there is no transference of the latency requirement from the master to the slave. Thus, all of the requests having the same priority are perceived by the slave to be of equal urgency. As such, in some instances, requests that are more latency critical may not be responded to in a timely manner.
When a master transmits a request to the arbitration system to access a slave, the master transmits a request signal to the arbitration system. As stated above, some transfer requests are latency critical, that is, there is a time constraint upon the fulfillment of the request. In these instances, a priority may be associated with the request. Regardless of the priority associated with the request, the arbitration system is unaware of the latency constraint, and thus, will manage each request identically, unless otherwise instructed.
To overcome the lack of identification of the latency requirement with the request, in some SOCs, a particular master will always be given highest priority regardless of the request. Since all of the requests from the particular master are given the highest priority, requests from the master that have a lower priority will be placed before higher priority requests from another master. In these instances, it is difficult to optimize the use of the bus.
To avoid starving requests from some masters in lieu of a specific master, the arbitration system in some SOCs will permit the masters to communicate with the slaves using a fair round robin scheme. For instance, a system comprising masters M0, M1. . . Mn, and slave S, prioritizes communication with the slave S as follows: M0, M1 . . . Mn; → M1 . . . Mn, M0; → . . . → Mn,M0 . . . Mn-1. Although this more evenly allows access to the slave by the masters, it fails to resolve the problems associated with requests of differing latency criteria.
Further issues arise as requests may be resident in an internal buffer prior to being granted by the arbitration system. Since the amount of elapsed time is not recognized by the arbiter, the request is transmitted without regard for the amount of time that has elapsed since the master initiated the request. Even though a request is granted by the arbiter, it may be transferred to another layer of interconnect or a bridging device and not the final target. Additionally, once the request is transmitted to the final target, it may be placed in a queue behind other earlier received requests regardless of the amount of time that has elapsed between the initial request and reaching the final target. In this regard, the latency requirement of the master may have expired prior to the request being acted upon.
A need in the industry exists which allows for the transfer of latency requirements appurtenant to a request from a requesting master to a slave. A further need exists for a system which can reprioritize a previously defined schedule for response to requests in accordance with the latency requirements of the requests, and thereby reduce transfer latency.